Staff Logic Design Engineer

Teledyne LeCroy

Milpitas, CA, US
Base: $141,900.00-$189,200.00; bonus/equity: not s...
7+ years digital logic design experience
Verilog/systemverilog rtl design proficiency
Pcie gen4/gen5/gen6 protocol knowledge
The role involves architecting and implementing high-performance digital logic for real-time decoding of high-speed protocols like PCIe and USB

Job Summary

  • The role involves architecting and implementing high-performance digital logic for real-time decoding of high-speed protocols like PCIe and USB.
  • Candidates will work on Xilinx Versal and Intel Agilex FPGAs to optimize latency, bandwidth, and resource efficiency for test and measurement products.
  • The team is described as dynamic, collaborative, and innovation-driven, focusing on validating cutting-edge technologies in data centers and AI/ML.

Matching Summary

The role involves architecting and implementing high-performance digital logic for real-time decoding of high-speed protocols like PCIe and USB.

Salary

Base: $141,900.00-$189,200.00; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • 7+ years digital logic design experience
  • Verilog/SystemVerilog RTL design proficiency
  • PCIe Gen4/Gen5/Gen6 protocol knowledge
  • Xilinx Versal or Intel Agilex FPGA development
  • SystemVerilog/UVM verification methodologies
  • High-speed serial protocol debugging skills

Nice-to-have

  • Python or Tcl scripting for automation
  • Experience with AXI interconnects
  • Hardware/software co-design background
  • Protocol analyzer product development history
  • SERDES link training and debug exposure

Key Requirements

  • BS in EE, CS, or Computer Engineering required
  • MS in EE preferred
  • 7+ years of FPGA or ASIC digital logic design experience

Work Rights

Not specified

Tailored Resume

Cover Letter