Senior Staff Engineer, Asic Design/implementation -- Lec/sta/power Analysis

Marvell

Base: $135,900 - $201,130 py; bonus/equity: not sp...
5-10 years asic timing experience
Sta signoff flow management
Primetime tool proficiency
This role focuses on developing and validating timing constraints for intricate SoC designs within Marvell's Photonic Fabric ecosystem

Job Summary

  • This role focuses on developing and validating timing constraints for intricate SoC designs within Marvell's Photonic Fabric ecosystem.
  • The successful candidate will own STA signoff methodologies, resolve tool issues, and automate flows using Tcl or Python.
  • Marvell offers comprehensive benefits including an employee stock purchase plan, family support programs, and robust mental health resources.

Matching Summary

This role focuses on developing and validating timing constraints for intricate SoC designs within Marvell's Photonic Fabric ecosystem.

Salary

Base: $135,900 - $201,130 per annum; Bonus/Equity: Not specified; Benefits: Stock purchase plan, family support, mental health resources

Skills & Requirements

Must-have

  • 5-10 years ASIC timing experience
  • STA signoff flow management
  • Primetime tool proficiency
  • Tcl or Python scripting skills
  • High-complexity silicon design knowledge

Nice-to-have

  • Experience with 5nm/4nm technology nodes
  • Deep understanding of TSMC N4/N5 processes
  • Strong cross-functional collaboration skills
  • Ability to create QoR dashboards and histograms

Key Requirements

  • Bachelor's degree plus 5-10 years experience OR Master's/PhD plus 3-5 years
  • Minimum 5 years industry experience in ASIC timing and STA
  • Eligibility to access export-controlled information under US law

Work Rights

Must be eligible to access export-controlled information (US citizen, LPR, or protected individual)

Tailored Resume

Cover Letter