Static timing analysis (sta) methodology development
Tcl and python scripting for flow automation
Synopsys primetime or cadence tempus expertise
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading STA flow development
Job Summary
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading STA flow development.
You will architect and maintain static timing analysis methodologies to support full-chip and hierarchical signoff for complex chips.
The position involves working hands-on with physical design partitions while collaborating across RTL, DFT, and P&R teams to resolve critical timing issues.
Matching Summary
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading STA flow development.
Skills & Requirements
Must-have
Static Timing Analysis (STA) methodology development
TCL and Python scripting for flow automation
Synopsys PrimeTime or Cadence Tempus expertise
SDC constraint management and validation
Multi-mode multi-corner (MMMC) timing signoff
Hierarchical timing closure for large-scale SoCs
Nice-to-have
Networking ASIC design experience
High-speed interface timing knowledge
Collaboration with global distributed teams
Power-aware timing flow exposure
Liberty modeling and silicon correlation
Version control systems like Git or Perforce
Key Requirements
B.S./M.S. in Electrical or Computer Engineering
6+ years of experience in ASIC/SoC timing analysis
Expertise in setup/hold, skew, OCV/AOCV/POCV analysis
Strong scripting skills in TCL, Python, and Makefiles