Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Creates Altera device-specific testcases with Verilog/VHDL and Altera IPs and verifies them for timing & functionality using industry-standard simulation and formal verification tools.
Collaborates with cross-functional teams to develop and improve Synthesis & Compiler test coverage and helps resolve customer issues as they occur.
Matching Summary
Validates and researches the Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
FPGA/ASIC RTL Design
VHDL, Verilog or SystemVerilog
Altera Quartus
FPGA Partial Reconfiguration (PR) flow
Hardware debugging skills
Simulation/Verification using VCS, Questa, XCelium
Timing Analysis (STA)
Shell, Perl, TCL or Python Scripting
Nice-to-have
cross-functional team collaboration
customer issue resolution
performance monitoring and assessment
Key Requirements
Min. 5+ years of relevant experience
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design
Experienced in FPGA Devices like Agilex, Virtex
Good experience with Hardware validation of FPGA Designs
Knowledge of bus protocols and High-Speed interfaces