Nvidia Corporation is seeking a Senior ASIC Engineer for their PMU and SECIP team in Shanghai, China. The role focuses on system-level ASIC design for critical GPU IPs, requiring strong collaboration across various teams and a solid foundation in front-end ASIC design
Job Summary
Analyze architectural requirements to define the Peregrine configuration for PMU, GSP, and SEC engines, including how each integrates into the GPU chip.
Develop essential wrapper logic as needed to bridge the Peregrine subsystem with each engine's interfaces.
Collaborate with the Physical Design team on partition assignment and floorplan considerations.
Matching Summary
Match Score: 85
Nvidia Corporation is seeking a Senior ASIC Engineer for their PMU and SECIP team in Shanghai, China. The role focuses on system-level ASIC design for critical GPU IPs, requiring strong collaboration across various teams and a solid foundation in front-end ASIC design.
Skills & Requirements
Must-have
system-level ASIC design
RTL coding
synthesis handoff
RISC-V subsystem integration
Nice-to-have
system-level chip integration
SoC-level design
embedded firmware workflows
multi-die / chiplet architectures
Key Requirements
BS or MS in Electrical Engineering or Computer Engineering