Semiconductor Digital Architect, Texas Institute For Electronics

The University of Texas at Austin

AUSTIN, TX, USA
Base: industry-competitive salaries; bonus/equity:...
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2.5d/3d microsystems architecture
High-bandwidth integration
Ai, hpc, wireless acceleration platforms
** The University of Texas at Austin is seeking a Semiconductor Digital Architect for the Texas Institute for Electronics, focusing on developing advanced digital subsystems for next-generation microsystems. This role emphasizes collaboration with industry partners and cross-disciplinary teams, requiring extensive experience in digital architecture and system design. **

Job Summary

  • The Texas Institute for Electronics (TIE) is a well-funded semiconductor foundry venture focused on advancing 3D heterogeneous integration and chiplet-based architectures.
  • The Semiconductor Digital Architect will develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.
  • UT Austin provides competitive health benefits, generous paid time off, a defined benefit retirement plan with employer matching, and robust training and discount programs.

Matching Summary

Match Score: 75

** The University of Texas at Austin is seeking a Semiconductor Digital Architect for the Texas Institute for Electronics, focusing on developing advanced digital subsystems for next-generation microsystems. This role emphasizes collaboration with industry partners and cross-disciplinary teams, requiring extensive experience in digital architecture and system design. **

Salary

Base: Industry-competitive salaries; Bonus/Equity: Not specified; Benefits: Competitive health benefits, retirement plan, paid time off

Skills & Requirements

Must-have

  • 2.5D/3D microsystems architecture
  • High-bandwidth integration
  • AI, HPC, wireless acceleration platforms
  • RTL design/verification
  • Hardware-software co-design
  • FPGA prototyping
  • Performance modeling
  • Architectural trade-off analysis

Nice-to-have

  • Industry partner engagement
  • Standards body engagement
  • Cross-disciplinary collaboration
  • Mentoring internal teams
  • Translating innovations into roadmaps

Key Requirements

  • Master’s of Science in Electrical or Computer Engineering
  • 12 years of experience in digital or system architecture
  • Strong exposure to AI, networking, or HPC accelerators
  • Deep expertise in dataflow architectures, memory hierarchies, interconnects, and compute optimization
  • Proficiency in SystemC, C++, or Python-based frameworks
  • Proven record of delivering complex digital design programs

Work Rights

Not specified

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