Senior Principal Functional Verification Engineer - Applied Ml

Cadence

San Jose, CA, US
Not specified; not specified; benefits include wel...
Formal verification experience
Systemverilog uvm methodology
Jasper xcelium eda tools
This role involves developing agentic AI solutions using LLMs to accelerate pre-silicon design verification processes

Job Summary

  • This role involves developing agentic AI solutions using LLMs to accelerate pre-silicon design verification processes.
  • The successful candidate will collaborate with machine learning engineers to validate the correctness and efficiency of autonomous chip design tools.
  • Cadence offers a culture focused on innovation, career development, and employee well-being within a Fortune 100 Best Companies environment.

Matching Summary

This role involves developing agentic AI solutions using LLMs to accelerate pre-silicon design verification processes.

Salary

Not specified; Not specified; Benefits include wellness policies and learning opportunities

Skills & Requirements

Must-have

  • Formal verification experience
  • SystemVerilog UVM methodology
  • Jasper Xcelium EDA tools
  • Python programming skills
  • Verilog debugging expertise

Nice-to-have

  • LLM and RAG framework knowledge
  • Agentic AI platform experience
  • Customer requirement engagement
  • Proactive problem-solving attitude
  • Continuous learning mindset

Key Requirements

  • BS degree with 10+ years experience
  • MS degree with 7+ years experience
  • PhD with 5+ years experience
  • 3+ years in ASIC verification methodologies
  • Advanced waveform viewer debugging skills

Work Rights

Not specified

Tailored Resume

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