Not specified (considering the job description does not provide specific work mode details).
Netlist-to-gds physical design implementation
12nm/6nm/4nm advanced process experience
Synopsys icc2 or cadence innovus tools
ALPSOFT TECHNOLOGIES PTE. LTD. is seeking a Senior Physical Design Engineer to oversee the Netlist-to-GDS physical design implementation for advanced process chips. The ideal candidate will have extensive experience with physical design, particularly in handling complex hierarchical chips
Job Summary
The role involves full responsibility for Netlist-to-GDS physical design implementation of advanced process chips ranging from 12nm to 4nm and below.
Candidates will act as block owners or TOP roles managing complex hierarchical chips with over 20 million instances and 500+ macros.
The position requires expertise in Synthesis, Auto Place and Route (APR), Signoff, and leading the full chip tapeout process.
Matching Summary
Match Score: 85
ALPSOFT TECHNOLOGIES PTE. LTD. is seeking a Senior Physical Design Engineer to oversee the Netlist-to-GDS physical design implementation for advanced process chips. The ideal candidate will have extensive experience with physical design, particularly in handling complex hierarchical chips.
Skills & Requirements
Must-have
Netlist-to-GDS physical design implementation
12nm/6nm/4nm advanced process experience
Synopsys ICC2 or Cadence Innovus tools
Perl TCL/TK script programming skills
Full chip tapeout responsibility
Nice-to-have
Block owner experience with 2-3 million instances
Hierarchical chip coordination for 50+ blocks
Critical issue resolution capabilities
Key Requirements
Bachelor/Master Degree in Electrical/Computer Engineering