The role involves reviewing design specifications to develop robust verification plans for high-performance data communication technologies
Job Summary
The role involves reviewing design specifications to develop robust verification plans for high-performance data communication technologies.
Engineers will build testbenches, run simulations, and debug failures to uncover design bugs in AI, networking, and storage systems.
The team fosters a collaborative culture where professionals are encouraged to take on new challenges and contribute to impactful semiconductor projects.
Matching Summary
The role involves reviewing design specifications to develop robust verification plans for high-performance data communication technologies.
Skills & Requirements
Must-have
SystemVerilog and UVM expertise
Constrained-random verification experience
SerDes PHY and DSP verification
Behavioral model creation for analog circuits
Python, Perl, C/C++, and GNU Make proficiency
Nice-to-have
Ethernet and PCIe protocol knowledge
Formal verification familiarity
Power-aware UPF verification techniques
Post-silicon validation support experience
Collaborative growth-oriented culture
Key Requirements
3 to 8 years of relevant design verification experience
Proficiency in SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make