Principal Engineer, Design Verification Engineering
Analog Devices Foundation
Bangalore, India
Soc/subsystem architectures
Verilog/systemverilog and uvm
Functional and code coverage
Lead design verification team for SOC or subsystem design pre silicon verification, formulating verification strategies and defining verification architecture, flow, methodology
Job Summary
Lead design verification team for SOC or subsystem design pre silicon verification, formulating verification strategies and defining verification architecture, flow, methodology.
Responsibilities include end-to-end SoC verification for complex digital SoCs, verifying microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced methodologies.
The role requires a B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
Matching Summary
Lead design verification team for SOC or subsystem design pre silicon verification, formulating verification strategies and defining verification architecture, flow, methodology.
Skills & Requirements
Must-have
SoC/Subsystem architectures
Verilog/SystemVerilog and UVM
Functional and code coverage
NoC, bus, and interconnect verification
Power-aware verification (UPF)
Formal verification techniques
High-speed and low-speed interfaces
Nice-to-have
Cross company technical initiatives
Patent and publish work
Mixed-signal/analog verification exposure
Problem-solving mindset
Learn and adopt new technologies
Key Requirements
12+ years of experience in digital pre-silicon verification