Senior RTL Design Engineer

AAC TECHNOLOGIES PTE. LTD.

Tampines, Singapore
Verilog hdl rtl design
I2c i2s soundwire interfaces
Uvm constrained random verification
The role involves designing mixed-signal subsystems from implementation to final delivery for chip-level integration

Job Summary

  • The role involves designing mixed-signal subsystems from implementation to final delivery for chip-level integration.
  • Candidates will perform micro-architectural studies to determine optimal hardware implementations for digital blocks.
  • The position requires supporting validation and bring-up of designs on silicon alongside cross-functional teams.

Matching Summary

The role involves designing mixed-signal subsystems from implementation to final delivery for chip-level integration.

Skills & Requirements

Must-have

  • Verilog HDL RTL design
  • I2C I2S SoundWire interfaces
  • UVM constrained random verification
  • Logic synthesis timing power analysis
  • Digital CMOS IC design experience

Nice-to-have

  • High-level modeling language proficiency
  • Spice co-simulation experience
  • FPGA emulation support
  • Cross-functional team collaboration
  • Silicon validation and bring-up

Key Requirements

  • Bachelor or Master degree in Electrical Engineering
  • Minimum 7+ years professional experience in digital CMOS IC design
  • Strong understanding of digital design interfaces

Work Rights

Not specified

Tailored Resume

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