Static Timing Analysis (sta) Engineer – (lead Or Senior)

The Boeing Company

El Segundo, CA, USA
Base: $146,200 – $239,200 depending on level; bonu...
100% onsite
5+ years timing closure experience on asics and fpgas
Proficiency with synopsys primetime or cadence tempus
Experience with rtl to gds flow and asic tape-out
This role involves handling pre-layout and post-layout timing for state-of-the-art digital ICs and FPGAs within Boeing's critical defense and security programs

Job Summary

  • This role involves handling pre-layout and post-layout timing for state-of-the-art digital ICs and FPGAs within Boeing's critical defense and security programs.
  • The position requires collaboration with global electronics groups to achieve first-pass success and timing convergence from early design stages through signoff.
  • Boeing offers a competitive total rewards package including variable compensation, health benefits, and an optional 9/80 work schedule rotation.

Matching Summary

This role involves handling pre-layout and post-layout timing for state-of-the-art digital ICs and FPGAs within Boeing's critical defense and security programs.

Salary

Base: $146,200 – $239,200 depending on level; Bonus/Equity: Variable compensation opportunities available; Benefits: Health insurance, retirement plans, paid time off

Skills & Requirements

Must-have

  • 5+ years timing closure experience on ASICs and FPGAs
  • Proficiency with Synopsys Primetime or Cadence Tempus
  • Experience with RTL to GDS flow and ASIC tape-out
  • Ability to generate tool-independent timing constraints
  • Programming skills in Python, TCL, Perl, or Unix shell

Nice-to-have

  • Experience leading static timing closure initiatives
  • Familiarity with space-based design and radiation mitigation
  • Knowledge of Synopsys Fusion Compiler and Formality tools
  • Understanding of Design for Testability (DFT) implications
  • Experience training new engineers in STA methodologies

Key Requirements

  • Bachelor of Science degree in Engineering or related field
  • U.S. Citizenship required for Top Secret Security Clearance
  • Minimum 5 years of experience with timing closure on ASICs/FPGAs
  • At least one successful ASIC tape-out experience required

Work Rights

Must have US citizenship

Tailored Resume

Cover Letter