Principle Application Engineer - Verification

BETA CAE Systems International AG

Shanghai, China
Uvm-based verification environments
Systemverilog
Constrained-random verification
Develop and execute verification plans for complex SoC subsystems and full-chip environments

Job Summary

  • Develop and execute verification plans for complex SoC subsystems and full-chip environments.
  • Build, enhance, and maintain UVM-based verification environments, including agents, sequences, scoreboards, and coverage models.
  • Collaborate closely with design, architecture, and validation teams to ensure design intent and testability.

Matching Summary

Develop and execute verification plans for complex SoC subsystems and full-chip environments.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • SystemVerilog
  • constrained-random verification
  • coverage-driven methodology
  • SoC architecture
  • debug functional issues

Nice-to-have

  • AI/ML hardware verification
  • Python, Perl, or shell scripting
  • post-silicon validation flows
  • low-power verification (UPF)
  • formal verification
  • performance validation

Key Requirements

  • 6+ years of hands-on experience
  • Bachelor’s/Master’s degree
  • experience verifying AP, AI accelerator, DSP, multimedia, or high-performance compute SoCs

Work Rights

Not specified

Tailored Resume

Cover Letter