Senior Logic Design Verification Engineer

Intel

Penang, Malaysia
8 years design verification experience
Uvm and system verilog expertise
Rtl model building and testbench development
The role involves validating next-generation architectural features for Intel's Power Management Controller IP

Job Summary

  • The role involves validating next-generation architectural features for Intel's Power Management Controller IP.
  • Candidates will collaborate with IP architects to define test plans and develop comprehensive verification environments.
  • This position requires cross-organizational influence with manufacturing and validation partners to resolve system-level issues.

Matching Summary

The role involves validating next-generation architectural features for Intel's Power Management Controller IP.

Skills & Requirements

Must-have

  • 8 years design verification experience
  • UVM and System Verilog expertise
  • RTL model building and testbench development

Nice-to-have

  • Formal Property verification skills
  • Strong analytical and debugging abilities
  • Agile methodology knowledge

Key Requirements

  • Bachelor's, Master's, or Ph.D. in Engineering
  • 8+ years relevant working experience
  • Experience with UVM Virtual Sequencer and Factory

Work Rights

Not specified

Tailored Resume

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