Asic Design & Verification Engineer

Cisco UK

Caesarea, Israel
**
Uvm based verification environment
Functional verification methodologies
Resolve bugs and achieve coverage closure
** Cisco UK is seeking an Asic Design & Verification Engineer to join their Silicon One Front-End Design team in Caesarea, Israel. The role involves chip design responsibilities, including verification and validation, utilizing advanced technologies and methodologies. Candidates should have a background in electrical engineering and experience with UVM and functional verification. **

Job Summary

  • Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development.
  • Implement Verification environment UVM based and collaborate with Design engineers to resolve bugs and achieve coverage closure.
  • Perform debug, root-cause analysis, and post-silicon validation in the lab.

Matching Summary

Match Score: 75

** Cisco UK is seeking an Asic Design & Verification Engineer to join their Silicon One Front-End Design team in Caesarea, Israel. The role involves chip design responsibilities, including verification and validation, utilizing advanced technologies and methodologies. Candidates should have a background in electrical engineering and experience with UVM and functional verification. **

Skills & Requirements

Must-have

  • UVM based verification environment
  • functional verification methodologies
  • resolve bugs and achieve coverage closure
  • verify chip flows
  • post-silicon validation

Nice-to-have

  • MATLAB simulations
  • bit-exact modeling environments
  • mixed-signal systems
  • Clock Domain Crossing (CDC)

Key Requirements

  • B.Sc./M.Sc. in Electrical Engineering
  • 3+ years of experience
  • knowledge with UVM
  • hands-on experience with CDC

Work Rights

Not specified

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