Ip Logic Design Engineer

Intel Retiree Medical Plan Trust

Bangalore, India
Hybrid
Digital io controllers
Pcie/cxl/ucie protocols
Rtl coding skills
The Data Centre-Design Silicon Engineering delivers leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs

Job Summary

  • The Data Centre-Design Silicon Engineering delivers leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs.
  • We are seeking an experienced Micro Architect/Senior Design Engineer to design, develop, and implement advanced Digital IO Controllers like PCIe/CXL/UCIe systems for next-generation data center and AI chips.
  • This role requires a unique blend of microarchitectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life.

Matching Summary

The Data Centre-Design Silicon Engineering delivers leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs.

Skills & Requirements

Must-have

  • Digital IO Controllers
  • PCIe/CXL/UCIe protocols
  • RTL coding skills
  • Memory coherency protocols
  • Interconnect topologies
  • High-speed clocking

Nice-to-have

  • Scalable memory coherency
  • Workload modeling
  • Emerging technologies
  • Problem-solving skills
  • Collaboration abilities

Key Requirements

  • Bachelor of Engineering with 8-12+ years experience
  • Master of Engineering with 7-11+ years experience
  • Digital design
  • System Verilog
  • RTL Design
  • FE RTL2Netlist methodology flows
  • STA
  • Formal Equivalence

Work Rights

Not specified

Tailored Resume

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