Signal And Power Integrity Technical Lead (hybrid)
Cisco UK
San Jose, CA, USA
$183,800.00 - $303,100.00; not specified; medical,...
56g pam4 and above expertise
High-speed serdes architectures
Channel modeling and ber prediction
Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products
Job Summary
Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
Matching Summary
Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Salary
$183,800.00 - $303,100.00; Not specified; Medical, dental, vision, 401(k), paid time off
Skills & Requirements
Must-have
56G PAM4 and above expertise
High-speed SerDes architectures
Channel modeling and BER prediction
Transmission line theory and electromagnetics
Keysight ADS, Ansys HFSS/EM flow
Cadence APD for layout review
Nice-to-have
Articulate technical concepts verbally and in writing
Experience with advanced nodes (5nm, 3nm)
High-bandwidth memory (HBM) SI
Die-to-die interfaces (UCIe)
Advanced packaging (CoWoS, EMIB)
MATLAB or Python scripting
Key Requirements
8+ years relevant SI/PI experience (Bachelor's)
6+ years relevant SI/PI experience (Master's)
3+ years relevant SI/PI experience (PhD)
Multiple high-speed ASIC tape-outs from package perspective