You will work on developing full chip & IP test methods, on-chip DFT (Design-for-Test) definition and verification, test vector generation and coverage analysis, ATE program development, and 1st Silicon debug for FPGA products
Job Summary
You will work on developing full chip & IP test methods, on-chip DFT (Design-for-Test) definition and verification, test vector generation and coverage analysis, ATE program development, and 1st Silicon debug for FPGA products.
Collaborate with worldwide cross-functional teams including designers, software, manufacturing, and product engineering, as you drive for test capability throughout the entire product development cycle.
Drive test optimization to reduce test cost, enhance product quality, improve manufacturing efficiency and accelerate manufacturing stability.
Matching Summary
You will work on developing full chip & IP test methods, on-chip DFT (Design-for-Test) definition and verification, test vector generation and coverage analysis, ATE program development, and 1st Silicon debug for FPGA products.
Skills & Requirements
Must-have
full chip & IP test methods
on-chip DFT definition and verification
test vector generation and coverage analysis
ATE program development
1st Silicon debug
CMT/ HDMT test module
STIL to pobj conversion
test program validation
Nice-to-have
academic exposure to IC Test Development
fault models
cross-functional team collaboration
Key Requirements
BS/MS in Electrical Engineering or equivalent
Solid understanding of digital and analog circuits
Strong programming in TCL/ PERL
Debugging/ problem solving skills
Malaysian citizens or hold relevant residence status
Work Rights
Malaysian citizens or hold relevant residence status