High Level Synthesis Compiler Engineer

Altera Digital Health

Toronto, Ontario, Canada
$139,000 – $201,250 cad; performance-based incenti...
Mlir and clang/llvm internals
C++ (modern standards)
Compiler design and optimization
Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang

Job Summary

  • Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang.
  • Architect and implement new compiler passes, analyses, and code transformations to improve synthesis quality and performance.
  • Analyze and optimize the compilation flow from C/C++/SYCL to hardware description languages.

Matching Summary

Lead the design, development, and optimization of HLS compiler infrastructure, focusing on MLIR and Clang.

Salary

$139,000 – $201,250 CAD; Performance-based incentive opportunities; Not specified

Skills & Requirements

Must-have

  • MLIR and Clang/LLVM internals
  • C++ (modern standards)
  • compiler design and optimization
  • HLS toolchains
  • parallelism and pipelining

Nice-to-have

  • MLIR or Clang open-source contributions
  • Verilog/VHDL experience
  • SYCL, OpenCL, CUDA knowledge
  • FPGA or ASIC design flows

Key Requirements

  • 5+ years compiler development experience
  • Strong HLS flows background
  • Proficiency in C++
  • Deep understanding of compiler optimization
  • Experience lowering high-level languages to hardware

Work Rights

Not specified

Tailored Resume

Cover Letter