Soc Physical Design Power Delivery Engineer

Intel

Bangalore, India
Hybrid
Block level full chip em ir analysis
Pdn signoff using redhawk rhsc voltus
Static ir dynamic ir vless checks
The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next-generation Server SoCs

Job Summary

  • The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next-generation Server SoCs.
  • Responsibilities include performing signal and power EM signoff analysis as well as validating IR drops using static and dynamic checks.
  • This role requires collaboration with SOC and Packaging teams to optimize bump assignments, RDL enablement, and package routing.

Matching Summary

The candidate will define the SoC level power delivery architecture and drive overall PDN convergence and signoff for next-generation Server SoCs.

Skills & Requirements

Must-have

  • Block level Full chip EM IR analysis
  • PDN Signoff using Redhawk RHSC Voltus
  • Static IR Dynamic IR Vless Checks
  • ESD analysis for High Performance SOCs
  • Tcl Perl Python scripting proficiency

Nice-to-have

  • Good knowledge on Power Delivery
  • Effective communication with global teams
  • Innovus RDL and Bump Planning familiarity

Key Requirements

  • Bachelors or Masters in Electrical Engineering
  • 8+ years experience in Block level Full chip EM IR
  • Hands-on experience with PDN Signoff tools

Work Rights

Not specified

Tailored Resume

Cover Letter