This role involves leading the architecture and design of complex SoC-wide clocking networks to optimize power-performance-area trade-offs
Job Summary
This role involves leading the architecture and design of complex SoC-wide clocking networks to optimize power-performance-area trade-offs.
The successful candidate will mentor a team while collaborating cross-functionally with RTL, physical design, and verification teams for end-to-end delivery.
You will partner with foundries and EDA vendors to ensure robust silicon correlation and yield for high-reliability products.
Matching Summary
This role involves leading the architecture and design of complex SoC-wide clocking networks to optimize power-performance-area trade-offs.
Skills & Requirements
Must-have
SoC clocking network architecture
PLL/DLL design and integration
Transistor-level circuit design
Clock tree synthesis (CTS)
Low-power techniques implementation
Glitch-free clock domain crossing
Nice-to-have
High-speed interface IP experience
Server AI/ML SoC background
Silicon bring-up and debug
Patents in circuit design
Custom memory design exposure
Key Requirements
M.Tech / B.Tech / Ph.D. in Electrical Engineering
15-20 years hands-on SoC clocking experience
Deep expertise in Spice simulations and post-layout validation
Experience leading multi-disciplinary global teams