Senior/staff Physical Design Engineer

Astera Labs

San Jose, CA, United States
Senior level: $135,000 - $165,000 usd; staff level...
On-site
Physical design tools and methodologies
Synthesis, place and route, timing
Block level ownership to gdsii
Oversee planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs

Job Summary

  • Oversee planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs.
  • Work closely with designers, verification engineering, and engineering operations to achieve design goals.
  • This role is fully on-site and in-person in San Jose, CA.

Matching Summary

Oversee planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs.

Salary

Senior Level: $135,000 - $165,000 USD; Staff Level: $160,000 - $195,000 USD

Skills & Requirements

Must-have

  • Physical design tools and methodologies
  • Synthesis, place and route, timing
  • Block level ownership to GDSII
  • Cadence and/or Synopsys tools
  • System Verilog/Verilog familiarity
  • Timing constraints and closure expertise
  • Working with IP vendors
  • Tcl, Python, or Perl scripting

Nice-to-have

  • Design for test knowledge
  • ECO methodologies and tools
  • LVS/DRC closures knowledge

Key Requirements

  • Bachelor’s degree in EE / Computer required
  • ≥3 years' experience in SoC/silicon products
  • 7nm or less technology experience
  • Professional attitude and ability to work with minimal guidance

Work Rights

Not specified

Tailored Resume

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