Rtl Design Principal Engineer

Marvell Technology

**
Verilog/system verilog rtl coding
Experience in asic design flow
Expertise in high speed protocols
** Marvell Technology is seeking a Principal Engineer for RTL Design to contribute to their innovative semiconductor solutions, particularly in high-performance data processing silicon platforms. The ideal candidate should have extensive experience in ASIC design, including architecture and micro-architecture specifications, with proficiency in Verilog/System Verilog and knowledge of high-speed protocols. **

Job Summary

  • Marvell’s semiconductor solutions are essential building blocks of data infrastructure.
  • The role involves defining subsystem architecture and implementing specifications using RTL coding techniques.
  • Marvell offers competitive compensation and a collaborative work environment.

Matching Summary

Match Score: 75

** Marvell Technology is seeking a Principal Engineer for RTL Design to contribute to their innovative semiconductor solutions, particularly in high-performance data processing silicon platforms. The ideal candidate should have extensive experience in ASIC design, including architecture and micro-architecture specifications, with proficiency in Verilog/System Verilog and knowledge of high-speed protocols. **

Skills & Requirements

Must-have

  • Verilog/System Verilog RTL coding
  • Experience in ASIC design flow
  • Expertise in high speed protocols

Nice-to-have

  • Experience with scripting in Perl/Python/Shell
  • Mentorship of junior team members
  • Collaboration with cross-functional teams

Key Requirements

  • Bachelor's or Master's degree in related fields
  • 12+ years of experience in relevant roles
  • Experience with complex SoC design

Work Rights

Not specified

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