Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing
Job Summary
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area.
Matching Summary
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Skills & Requirements
Must-have
physical design flow
EDA tools
STA flow
LEC flow
ERC flow
DRC flow
scripting languages
Nice-to-have
low power design methodologies
multiple clock domains
power management
mentoring junior team members
analytical problem solving skills
Key Requirements
5+ years relevant experience
multiple tape-out experience
deep submicron process nodes
VHDL and Verilog knowledge
Bachelor's degree in computer engineering or related field