Ip Design Verification Engineer

Intel Corporation

Hillsboro, Oregon, US
Base: $122,440.00-232,190.00 usd; bonus/equity: st...
Hybrid
System verilog & uvm testbench development
Verification environments and coverage metrics
Constrained-random stimulus and coverage closure
Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements

Job Summary

  • Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.
  • Develop and execute detailed verification plans, test benches, and verification environments with comprehensive coverage metrics.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • System Verilog & UVM testbench development
  • Verification environments and coverage metrics
  • Constrained-random stimulus and coverage closure
  • Debugging presilicon environments
  • Functional verification infrastructure maintenance

Nice-to-have

  • AI/ML-driven verification innovation
  • Custom automation script development
  • Evaluating new verification technologies
  • Formal verification techniques
  • Power-aware verification experience

Key Requirements

  • 6+ years experience in digital design verification
  • Bachelor's degree in EE, CE, CS, or related
  • Experience with Python or other scripting languages
  • Experience with Synopsys VCS, Cadence Xcelium, or Mentor Questa
  • Experience with version control systems (Git, Perforce)

Work Rights

Not specified

Tailored Resume

Cover Letter