This role involves architecting and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products
Job Summary
This role involves architecting and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products.
The successful candidate will drive metric-driven verification to full closure while collaborating with world-class teams across Design, Architecture, and Validation.
You will define robust verification strategies including directed, constrained random, and formal methods for IP, Sub-System, and SoC verification.
Matching Summary
This role involves architecting and maintaining advanced UVM-based and C-based verification environments for next-generation automotive products.
Skills & Requirements
Must-have
UVM based verification environments
SystemVerilog testbench development
ASIC SoC verification experience
Directed and constrained random stimulus
Low power verification UPF CPF flow
SVA assertion development
C/C++ Perl Python scripting
Nice-to-have
Formal verification methodology
Gate level timing simulation
FPGA prototyping experience
Collaboration with analog design teams
Metric driven verification closure
Key Requirements
B.S./M.S. in Electrical or Computer Engineering
8+ years of ASIC/SoC verification experience
Proven track record taking chips from specification to tape out