Principal Verification Engineer

Altera

New Delhi, India
Fully remote
Systemverilog and uvm verification environments
10+ years asic or fpga design verification experience
Developing drivers, monitors, scoreboards, and checkers
The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects

Job Summary

  • The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects.
  • Candidates will develop robust, reusable verification environments using SystemVerilog and UVM to exercise design functionality and uncover bugs.
  • The position requires defining and tracking functional and code coverage metrics to ensure verification completeness and drive closure.

Matching Summary

The role involves collaborating with architects and design engineers to define comprehensive verification strategies for FPGA acceleration projects.

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification environments
  • 10+ years ASIC or FPGA design verification experience
  • Developing drivers, monitors, scoreboards, and checkers
  • Executing simulation regressions and root cause analysis
  • Defining functional and code coverage metrics

Nice-to-have

  • Familiarity with AMBA protocols like AXI and PCIe
  • Experience with formal verification methods
  • Strong Python or Perl scripting skills
  • Collaborative cross-functional team environment

Key Requirements

  • Bachelor's or master's degree in electrical engineering
  • 10+ years of experience in ASIC or FPGA verification
  • Expertise in Verilog, VHDL, and SystemVerilog
  • Proficiency in modern verification methodologies including CDV and ABV

Work Rights

Not specified

Tailored Resume

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