Senior Principal Dft Engineer

NXP USA INC.

12+ years dft experience
Mentor/synopsys test generation tools
Scan compression and mbist design
The candidate will architect DFT design and manage instrument insertion and simulation for the Pune MCU team

Job Summary

  • The candidate will architect DFT design and manage instrument insertion and simulation for the Pune MCU team.
  • Responsibilities include collaborating with BE leads for STA, working with physical design teams to close timing, and guiding junior engineers.
  • The role requires bringing up test patterns on silicon and ensuring all DFT requirements are met for sign-off.

Matching Summary

The candidate will architect DFT design and manage instrument insertion and simulation for the Pune MCU team.

Skills & Requirements

Must-have

  • 12+ years DFT experience
  • Mentor/Synopsys test generation tools
  • Scan compression and MBIST design
  • JTAG and IEEE 1500 Standard knowledge
  • SOC lead and production DFT experience
  • STA and IR drop analysis collaboration

Nice-to-have

  • Tessent shell flow expertise
  • Yield estimation and optimization
  • Lab and test floor bring-up debug
  • Synthesis and back-end implementation flows
  • DFT AI mindset application
  • Logic diagnosis skills

Key Requirements

  • BE/MS degree in Electronics/Electrical/Computer Engineering
  • Minimum 12+ years of DFT experience
  • Hands-on expertise with Mentor/Synopsys tools
  • Proven DFT lead experience for complex SOC TO and Production

Work Rights

Not specified

Tailored Resume

Cover Letter