Job Summary

• Lead the global, mission-critical infrastructure that powers Cadence's EDA tools development, enables customers to design and verify the world's most advanced semiconductors faster and more reliably.
• Oversee global data centers and execute a hybrid cloud strategy that enables seamless capacity bursting during peak design, verification, and emulation cycles.
• Partner closely with EDA R&D leaders to align infrastructure roadmaps with next-generation analog, digital, mixed-signal, verification, and emulation technologies.

Matching Summary

Salary

Base: $185,500 to $344,500; Bonus/Equity: Eligible for incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k) with match, ESPP, medical, dental, vision

Skills & Requirements

Key Requirements

• 15+ years of leadership experience
• Expert-level Linux/Unix knowledge
• High-performance networking knowledge
• Enterprise-class storage architectures
• Deep understanding of semiconductor design flows
• Proven ability to lead global teams
• Bachelor’s degree in Computer Science or related field

Work Rights