Senior Staff Asic Design Egineer - Ai/ml Hardware Ip Category Location Toronto, Ontario

Talentlab Inc

Toronto, Ontario, Canada
On-site
6+ years asic design experience
Advanced verilog/systemverilog skills
Complex soc block ownership
This role involves defining micro-architecture and implementing RTL for cutting-edge AI/ML hardware IP

Job Summary

  • This role involves defining micro-architecture and implementing RTL for cutting-edge AI/ML hardware IP.
  • The engineer will drive linting, CDC, synthesis, and power intent flow execution while optimizing performance and area.
  • Candidates must partner closely with verification teams to develop test plans and SVA assertions for formal strategies.

Matching Summary

This role involves defining micro-architecture and implementing RTL for cutting-edge AI/ML hardware IP.

Skills & Requirements

Must-have

  • 6+ years ASIC design experience
  • Advanced Verilog/SystemVerilog skills
  • Complex SoC block ownership
  • Clock/reset and FIFO architecture
  • Power-aware design with UPF
  • AXI bus protocol knowledge
  • AI/ML hardware acceleration blocks

Nice-to-have

  • Python scripting for automation
  • Formal verification strategies
  • Cross-functional leadership
  • Best practices promotion
  • TCL and Perl scripting

Key Requirements

  • Bachelor's, Master's, or PhD in Electrical Engineering
  • Must be legally authorized to work on-site in Canada

Work Rights

Must have legal authorization to work on-site in Canada

Tailored Resume

Cover Letter