Senior Principal Application Engineer

Cadence

Burlington, MA, United States
Base: $133,000 to $247,000; bonus/equity: incentiv...
Cadence verification platforms
Ai assistants, agentic ai, machine learning
Customer facing technical support
Join an elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!

Job Summary

  • Join an elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!
  • As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning.
  • The skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.

Matching Summary

Join an elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!

Salary

Base: $133,000 to $247,000; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k) with match, ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • Cadence verification platforms
  • AI assistants, Agentic AI, machine learning
  • customer facing technical support
  • SystemVerilog, VHDL, Verilog
  • UVM testbench architecture
  • RTL and Testbench debug skills
  • scripting (Perl, Python, Tcl)

Nice-to-have

  • innovative solutions
  • customer success ownership
  • technical leadership roles
  • energy and enthusiasm

Key Requirements

  • BS, MS, or PhD degree
  • 5+ years experience
  • SystemVerilog, VHDL, Verilog
  • UVM testbench architecture
  • RTL and Testbench debug skills
  • scripting (Perl, Python, Tcl)
  • software, HDL design and verification skills

Work Rights

Not specified

Tailored Resume

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