Asic Physical Design Engineer

Cisco UK

Yerevan, Armenia
Hybrid
Rtl-to-gdsii physical implementation
5+ years asic physical design experience
Synopsys or cadence pnr tools
The team specializes in macro-level RTL-to-GDSII physical implementation and signoff for complex SoC projects

Job Summary

  • The team specializes in macro-level RTL-to-GDSII physical implementation and signoff for complex SoC projects.
  • Engineers will perform synthesis, floorplanning, placement, CTS, and routing while optimizing power, performance, and area.
  • This hybrid role requires four days per week at Cisco's Yerevan office to collaborate closely with front-end teams.

Matching Summary

The team specializes in macro-level RTL-to-GDSII physical implementation and signoff for complex SoC projects.

Skills & Requirements

Must-have

  • RTL-to-GDSII physical implementation
  • 5+ years ASIC physical design experience
  • Synopsys or Cadence PnR tools
  • Static timing analysis (STA)
  • Clock Tree Synthesis (CTS) and routing

Nice-to-have

  • Scripting proficiency in Tcl or Python
  • Electromigration and IR-drop optimization
  • Collaboration with Front-End teams
  • Formal verification expertise
  • Block-level synthesis knowledge

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • 5+ years of hands-on experience in ASIC design
  • Proven track record in complex SoC or block-level projects

Work Rights

Not specified

Tailored Resume

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