Job Summary

• Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
• Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
• The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).

Matching Summary

Skills & Requirements

Key Requirements

• BE/B.Tech with 12 years experience OR ME/M.Tech with 10 years experience
• Verilog/System Verilog IP verification experience
• UVM coding experience
• DDR4/DDR5/LP5/LP6 protocol expertise
• Low-power design using UPF
• Simulation and debug experience using VCS/Verdi
• Checker development
• Verification environment development
• Integrating BFM/Checkers
• Subsystem to SoC Integration
• Writing Test plans and testcases
• Coding Coverage and assertions
• Mixed signal verification exposure
• GLS verification exposure

Work Rights