Fpga Silicon Design Verification Engineer

Altera Corporation

Bengaluru, Karnataka, India
Systemverilog experience
Uvm or ovm methodology
Perl or python scripting
The role involves architecting effective testbench and verification strategies to promote debug and failure detection

Job Summary

  • The role involves architecting effective testbench and verification strategies to promote debug and failure detection.
  • Candidates will build UVM infrastructure including monitors, drivers, and scoreboards while producing functional and code coverage.
  • The position requires developing constrained random stimulus to effectively stress the design space and ensure functional correctness.

Matching Summary

The role involves architecting effective testbench and verification strategies to promote debug and failure detection.

Skills & Requirements

Must-have

  • SystemVerilog experience
  • UVM or OVM methodology
  • Perl or Python scripting

Nice-to-have

  • C/C++ golden model comparison
  • Ethernet PCIE AXI DDR protocols
  • Reusable component development

Key Requirements

  • Bachelor's Degree in Electrical or Computer Engineering
  • Minimum 5 years of relevant experience
  • Experience with multiple RTL simulators

Work Rights

Not specified

Tailored Resume

Cover Letter