Principal Engineer, Design Technology Co-optimization

Inteelabs

Hillsboro, Oregon, US
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
Hybrid
Advanced semiconductor technology understanding
Foundation ip design and dtco
Standard cell library design
As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs

Job Summary

  • As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.
  • Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • Advanced semiconductor technology understanding
  • Foundation IP design and DTCO
  • Standard cell library design
  • MOSFET electrical characteristics
  • Library cell characterization methodology
  • Semiconductor foundry ecosystem experience

Nice-to-have

  • Product design signoff methodology
  • Pre and post Si foundry benchmarking
  • EDA tool design and optimization
  • Foundation IP Si validation

Key Requirements

  • 10+ years industry experience
  • Ph.D. or Master's degree
  • Excellent oral and written communication
  • Technical leadership and delivery track record

Work Rights

Not specified

Tailored Resume

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