Sr Principal Design Verification Engineer - Soc Verification

NXP USA INC.

System verilog, uvm methodology
Bus protocols (ahb, axi, chi, ace, apb)
Processor architecture, cache coherency
The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities

Job Summary

  • The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.
  • The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis.
  • Work with peer teams to correlate performance metrics across different platforms (TLM, RTL, Emulation, Silicon validation, applications).

Matching Summary

The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.

Skills & Requirements

Must-have

  • System Verilog, UVM methodology
  • Bus Protocols (AHB, AXI, CHI, ACE, APB)
  • Processor architecture, cache coherency
  • Memory subsystems, DDR controllers
  • Performance verification scenarios
  • Debug, failure re-creation, root cause analysis

Nice-to-have

  • Emulation platform execution and debug
  • Domain knowledge in Graphics/Multimedia/Networking IPs

Key Requirements

  • Experience with HDL/HVL
  • Strong understanding of Bus Protocols
  • Understanding of processor architecture
  • Understanding of memory subsystems
  • Programming skills in C/C++/Python
  • Domain knowledge in Graphics/Multimedia/Networking IPs

Work Rights

Not specified

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