Asic Engineer

Jane Street

London, United Kingdom
On-site
4+ years practical experience in rtl design
Experience with synopsys or cadence flows
Front-end rtl design and synthesis skills
The role involves collaborating across trading, networking, and research infrastructure teams within the Ultra Low Latency group

Job Summary

  • The role involves collaborating across trading, networking, and research infrastructure teams within the Ultra Low Latency group.
  • Candidates will work on both FPGA-based and ASIC-based technologies to design and deploy advanced hardware solutions.
  • The company values better tools for productivity and offers training in their custom Hardcaml development toolchain.

Matching Summary

The role involves collaborating across trading, networking, and research infrastructure teams within the Ultra Low Latency group.

Skills & Requirements

Must-have

  • 4+ years practical experience in RTL design
  • Experience with Synopsys or Cadence flows
  • Front-end RTL design and synthesis skills
  • Back-end physical design expertise
  • Verification including formal verification methods

Nice-to-have

  • Interest in software engineering for hardware
  • Programming experience in Python C++ Java Haskell
  • Willingness to learn OCaml language
  • Excitement about improving tool productivity

Key Requirements

  • Minimum 4 years of practical experience in RTL design and verification
  • Proficiency in ASIC design flows using Synopsys or Cadence
  • Fluent English communication skills required

Work Rights

Not specified

Tailored Resume

Cover Letter