Lead Design Engineer

BETA CAE Systems International AG

Hyderabad, India
Foundry rule decks and technology files
Pdk qa, verification and release methodology
Physical verification methodology development
Develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point

Job Summary

  • Develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
  • Responsible for physical verification methodology, including installation, development, qualification, automation, and support.
  • Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment.

Matching Summary

Develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.

Skills & Requirements

Must-have

  • Foundry rule decks and technology files
  • PDK QA, verification and release methodology
  • Physical verification methodology development
  • Automate LVS, DRC, RM, IR
  • Cadence Python, SKILL, Perl programming
  • Deep sub-micron CMOS processes
  • Cadence custom IC Virtuoso platform

Nice-to-have

  • Excellent technical problem solving skills
  • Excellent communication and presentation skills
  • Pcell creation and enhancements
  • Physical verification tools for DRC, LVS

Key Requirements

  • Bachelor’s Degree in Electrical/Electronic Engineering
  • 4-7 years of Work experience in PDK development
  • Experience with Cadence custom IC Virtuoso platform
  • Experience in developing PDK device library components
  • Working knowledge of revision control software

Work Rights

Not specified

Tailored Resume

Cover Letter