Asic/fpga Verification Engineer (experienced, Lead, Or Senior)

Boeing Aerostructures Australia

El Segundo, CA, US
Experienced (level 3): $119,850 - $162,150; lead (...
100% onsite
Uvm & system verilog
Object-oriented programming principles
Functional coverage models
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog

Job Summary

  • Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
  • Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
  • Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.

Matching Summary

Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.

Salary

Experienced (Level 3): $119,850 - $162,150; Lead (Level 4): $126,650 - $171,350 / $146,200 - $197,800; Senior (Level 5): $176,800 - $239,200

Skills & Requirements

Must-have

  • UVM & System Verilog
  • Object-Oriented Programming principles
  • Functional Coverage Models
  • Code Coverage analysis
  • FPGA-based prototyping
  • Linux Environments

Nice-to-have

  • hardware emulators, especially Palladium
  • high-speed Serdes interfaces
  • space-based design techniques
  • radiation mitigation
  • 1st pass success with ASIC designs

Key Requirements

  • Bachelor of Science degree in Engineering or related field
  • 5+ years of ASIC/FPGA verification experience
  • Proficiency in SystemVerilog and SystemVerilog Assertions
  • Ability to obtain a US Security Clearance
  • US Citizenship required for Security Clearance

Work Rights

US Security Clearance required

Tailored Resume

Cover Letter