Front End Asic Rtl/logic Verification Engineer

Altera

Penang, Malaysia
**
Rtl coding using hdl languages
Logic simulation and debug environments
Verification plan development
** Altera is seeking a Front End ASIC RTL/Logic Verification Engineer in Penang, Malaysia. The role involves developing verification plans, ensuring design features are correctly verified, and supporting SoC customers for high-quality integration. **

Job Summary

  • The role involves developing verification plans to ensure design features are correctly verified.
  • Candidates will support SoC customers to ensure high-quality integration and verification of the IP block.
  • The position requires driving quality assurance compliance for smooth IP-SoC handoff.

Matching Summary

Match Score: 75

** Altera is seeking a Front End ASIC RTL/Logic Verification Engineer in Penang, Malaysia. The role involves developing verification plans, ensuring design features are correctly verified, and supporting SoC customers for high-quality integration. **

Skills & Requirements

Must-have

  • RTL coding using HDL languages
  • Logic simulation and debug environments
  • Verification plan development

Nice-to-have

  • Scripting knowledge
  • Strong communication skills
  • Leadership and problem solving abilities

Key Requirements

  • BS/MS or PhD in Electronics Engineering
  • Proficiency with RTL coding
  • Familiarity with logic simulation

Work Rights

Not specified

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