Define, implement, and maintain DFT strategies for FPGA designs to meet quality, coverage, and manufacturability goals
Job Summary
Define, implement, and maintain DFT strategies for FPGA designs to meet quality, coverage, and manufacturability goals.
Collaborate closely with Front End IP Design & Physical Design teams to meet timing closure for DFT paths and resolve congestion, clocking, and scan-related issues.
Develop, improve, and document DFT methodologies and best practices, mentoring junior engineers and participating in architecture reviews.
Matching Summary
Define, implement, and maintain DFT strategies for FPGA designs to meet quality, coverage, and manufacturability goals.
Skills & Requirements
Must-have
DFT strategies for FPGA designs
Scan Architecture and Insertion
ATPG pattern generation and coverage
Cell-Aware, Power Aware DFT
Memory BIST and Repair
Streaming Scan Network (SSN)
IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG)
Nice-to-have
AI or LLM implementations in FPGA
Functional Safety standards knowledge
Post-silicon debug and yield learning
ATE platforms and production test
Low-power DFT techniques
DFT automation or flow development
Cross-site or global team experience
Key Requirements
7+ years of industry experience in DFT design
Bachelor’s or Master’s degree in Electrical / Electronic Engineering
Solid understanding of DFT methodologies and fault models