Applied Ml - Functional Verification Engineer

Cadence

San Jose, California, United States
Base: $154,000 to $286,000; bonus/equity: eligible...
Pre-silicon asic verification experience
Formal verification or uvm methodology expertise
Advanced debugging with waveform viewers
This role involves developing agentic AI solutions using LLMs to autonomously design and verify chips with significant productivity gains

Job Summary

  • This role involves developing agentic AI solutions using LLMs to autonomously design and verify chips with significant productivity gains.
  • Candidates will collaborate with machine learning engineers and software teams to validate the correctness and efficiency of AI-enhanced verification methodologies.
  • The position offers a competitive salary range of $154,000 to $286,000 along with comprehensive benefits including equity and incentive compensation.

Matching Summary

This role involves developing agentic AI solutions using LLMs to autonomously design and verify chips with significant productivity gains.

Salary

Base: $154,000 to $286,000; Bonus/Equity: Eligible for incentive compensation; Benefits: 401(k) match, medical, dental, vision, stock purchase plan

Skills & Requirements

Must-have

  • Pre-silicon ASIC verification experience
  • Formal verification or UVM methodology expertise
  • Advanced debugging with waveform viewers
  • Hands-on EDA tools like Jasper or Xcelium
  • Strong programming in Verilog SystemVerilog Python

Nice-to-have

  • Experience with LLMs and ML technologies
  • Knowledge of RAG RFT RL frameworks
  • Agentic AI framework exposure
  • Customer engagement and requirements gathering
  • Proactive problem solving and continuous learning

Key Requirements

  • BS degree with 10+ years experience OR MS with 7+ years OR PhD with 5+ years
  • Minimum 3 years in pre-silicon ASIC verification methodologies
  • Location: San Jose, CA

Work Rights

Not specified

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