Cpu Core Senior Physical Design Engineer

Intel

Folsom, California, United States
Base: $164,470.00-232,190.00 usd; bonus/equity: st...
Hybrid
Vlsi circuit design and synthesis
Static timing analysis
Low power design
Intel is seeking a Senior Physical Design Engineer with expertise in CPU design, focusing on the physical design flow from RTL to GDS, including synthesis, static timing analysis, and power distribution. The role is hybrid and requires significant experience in VLSI design, with a strong preference for candidates familiar with x86 architecture and programming skills in Tcl/Perl/Python

Job Summary

  • The role involves performing physical design implementation of custom CPU designs from RTL to GDS to create a manufacturing-ready design database.
  • Candidates will optimize CPU design parameters such as power, frequency, and area while collaborating with logic, circuit, and architecture teams.
  • Intel offers a competitive compensation package including stock bonuses and comprehensive health, retirement, and vacation benefits.

Matching Summary

Match Score: 85

Intel is seeking a Senior Physical Design Engineer with expertise in CPU design, focusing on the physical design flow from RTL to GDS, including synthesis, static timing analysis, and power distribution. The role is hybrid and requires significant experience in VLSI design, with a strong preference for candidates familiar with x86 architecture and programming skills in Tcl/Perl/Python.

Salary

Base: $164,470.00-232,190.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • VLSI circuit design and synthesis
  • Static timing analysis
  • Low power design
  • CPU physical design flow
  • Clock tree synthesis

Nice-to-have

  • x86 CPU architecture experience
  • Tcl Perl Python programming
  • EDA vendor collaboration
  • Power domain analysis expertise

Key Requirements

  • Bachelor's degree in STEM with 6+ years experience OR Master's with 4+ years
  • Experience in VLSI circuit design and synthesis
  • Proficiency in static timing analysis and low power design

Work Rights

Not specified

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