Principal Design Verification Engineer

Astera Labs

San Jose, California, United States
Base: $185,000 to $230,000; bonus/equity: eligible...
On-site
Systemverilog and uvm expertise
8+ years soc verification experience
Server and networking application background
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies

Job Summary

  • Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.
  • The role involves leading the full lifecycle verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
  • This position offers a competitive salary range of $185,000 to $230,000 with eligibility for discretionary bonuses, incentives, and benefits.

Matching Summary

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

Salary

Base: $185,000 to $230,000; Bonus/Equity: Eligible for discretionary bonus and incentives; Benefits: Not specified

Skills & Requirements

Must-have

  • SystemVerilog and UVM expertise
  • 8+ years SoC verification experience
  • Server and networking application background
  • Full verification lifecycle management
  • Directed and constrained-random techniques

Nice-to-have

  • Third-party Verification IP experience
  • Network-on-Chip architecture knowledge
  • Emulation platform and co-verification skills
  • Ethernet/PCIe switching architecture familiarity
  • Strong independent problem-solving abilities

Key Requirements

  • Bachelor's degree in Electrical Engineering (Master's preferred)
  • 8+ years of experience in SoC verification
  • Proficiency with industry-standard simulators and regression systems

Work Rights

Not specified

Tailored Resume

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