Asic Verification Lead/architect

Atos SE

Bangalore, IN
On-site
Uvm verification framework
Constraint-random, coverage driven methodology
Systemverilog / c++ development
Integrating ASIC functional verification team for network controllers, routers, and cache coherence controllers targeting Bull high-end servers

Job Summary

  • Integrating ASIC functional verification team for network controllers, routers, and cache coherence controllers targeting Bull high-end servers.
  • Develop, maintain, and publish verification specifications, and monitor, analyze, and debug simulation errors.
  • Monitor and analyze simulation coverage results to improve tests and achieve coverage targets on time.

Matching Summary

Integrating ASIC functional verification team for network controllers, routers, and cache coherence controllers targeting Bull high-end servers.

Skills & Requirements

Must-have

  • UVM verification framework
  • Constraint-Random, Coverage Driven methodology
  • SystemVerilog / C++ development
  • simulation tools and coverage visualization

Nice-to-have

  • mentoring junior engineers
  • improving processes and methodologies

Key Requirements

  • 8+ years of experience
  • Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)
  • Mastering UVM or equivalent verification methodology
  • Experience in managing tasks for a small team

Work Rights

Not specified

Tailored Resume

Cover Letter