The candidate will be engaged with Design, Architecture, FW/SW, driver development team and more to develop design models for validation and verification
Job Summary
The candidate will be engaged with Design, Architecture, FW/SW, driver development team and more to develop design models for validation and verification.
Create FPGA and Hybrid FPGA emulation models from RTL using FPGA synthesis, partitioning and routing tools.
We offer a total compensation package that ranks among the best in the industry.
Matching Summary
The candidate will be engaged with Design, Architecture, FW/SW, driver development team and more to develop design models for validation and verification.
Salary
Base: $122,440.00-232,190.00 USD; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
FPGA and Emulation
RTL coding
hybrid models
Nice-to-have
Linux experience
Wireless and Networking Protocols
PCIE knowledge
Key Requirements
Bachelor's and 6+ years or Master's and 5+ years in Electrical/Electronic Engineering, Computer Engineering, Computer Science or Communications and Electronic Engineering