Asic Engineering Technical Lead - Dft

Cisco UK

Base: $183,800.00 to $263,600.00; bonus/equity: el...
Not specified
Asic design-for-test (dft) experience
Scan insertion and compression logic
Siemens tessent or synopsys tool proficiency
Cisco UK is seeking an ASIC Engineering Technical Lead specializing in Design-for-Test (DFT) for their Acacia team, which focuses on innovative silicon-based optical interconnect products. The ideal candidate will have extensive experience in ASICs and DFT architectures, and the position offers a robust salary along with a range of benefits in a collaborative and inclusive work environment

Job Summary

  • The role involves leading the development of DFT solutions for next-generation ASICs used in multi-100G to 1.6T coherent optical communications products.
  • Candidates will be responsible for implementing hierarchical test flow architectures including scan insertion, memory BIST, and logic BIST using industry-standard tools.
  • Cisco offers a comprehensive benefits package including medical, dental, vision insurance, 401(k) matching, and flexible vacation time for exempt employees.

Matching Summary

Match Score: 85

Cisco UK is seeking an ASIC Engineering Technical Lead specializing in Design-for-Test (DFT) for their Acacia team, which focuses on innovative silicon-based optical interconnect products. The ideal candidate will have extensive experience in ASICs and DFT architectures, and the position offers a robust salary along with a range of benefits in a collaborative and inclusive work environment.

Salary

Base: $183,800.00 to $263,600.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), paid leave

Skills & Requirements

Must-have

  • ASIC Design-for-Test (DFT) experience
  • Scan insertion and compression logic
  • Siemens Tessent or Synopsys tool proficiency
  • ATPG test pattern generation
  • Python, Tcl, or C++ automation skills

Nice-to-have

  • Experience with ATE testers and test teams
  • Debugging clock domain crossings
  • Knowledge of advanced silicon process nodes
  • Verilog/System Verilog design block integration
  • Cross-functional team leadership

Key Requirements

  • Bachelor's degree plus 8 years of related experience
  • Prior experience working with ASICs
  • Proven track record in scan insertion and DFT setup
  • Experience driving DFT execution from concept through tapeout

Work Rights

Not specified

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