Fpga Sw Validation Engineer - Synthesis

Altera

Bengaluru, Karnataka, India
Fpga/asic rtl design verification
Verilog vhdl systemverilog experience
Partial reconfiguration pr flow knowledge
The role involves validating and researching Quartus Synthesis & Compiler optimizations alongside Partial Reconfiguration flows

Job Summary

  • The role involves validating and researching Quartus Synthesis & Compiler optimizations alongside Partial Reconfiguration flows.
  • Candidates must create device-specific testcases using Verilog or VHDL and verify them for timing and functionality.
  • The position requires collaborating with cross-functional teams to improve test coverage and resolve customer issues.

Matching Summary

The role involves validating and researching Quartus Synthesis & Compiler optimizations alongside Partial Reconfiguration flows.

Skills & Requirements

Must-have

  • FPGA/ASIC RTL Design verification
  • Verilog VHDL SystemVerilog experience
  • Partial Reconfiguration PR flow knowledge
  • SignalTap ChipScope HW debugging skills
  • VCS Questa XCelium simulation tools
  • STA timing analysis expertise
  • Shell Perl TCL Python scripting

Nice-to-have

  • Cross-functional team collaboration
  • Customer issue resolution support
  • Agilex Virtex device familiarity
  • Synplify tool experience
  • High-speed interface protocols

Key Requirements

  • Minimum 5+ years of relevant FPGA/ASIC experience
  • Master's or Bachelor's degree in Electronics/VLSI/Digital Design
  • Knowledge of AHB AXI PCIe Ethernet Avalon bus protocols

Work Rights

Not specified

Tailored Resume

Cover Letter