Dfx Design Architect

Indclutch

Penang, Malaysia
**
10-12 years dft/dfd experience
Hierarchical dft and scan compression
Ieee 1687 and ieee 1838 standards
** Indclutch is seeking a DFX Design Architect for its Penang location, focusing on developing strategies for Design for Test (DFT) and Design for Debug (DFD) in advanced FPGA and SoC systems. The role demands extensive experience in semiconductor product life cycles and offers leadership opportunities, technical mentorship, and collaboration across global teams. **

Job Summary

  • This role serves as the technical authority defining the overarching strategy for Design for Test and Debug across Altera's next-generation FPGA and SoC families.
  • The architect will drive the adoption of advanced DFX features including IEEE 1687, IEEE 1838, and High-Speed Link Testing to minimize test costs and accelerate time-to-market.
  • Candidates must possess deep expertise in multi-die chiplet systems, silicon debug, and cross-functional collaboration with global manufacturing and design teams.

Matching Summary

Match Score: 75

** Indclutch is seeking a DFX Design Architect for its Penang location, focusing on developing strategies for Design for Test (DFT) and Design for Debug (DFD) in advanced FPGA and SoC systems. The role demands extensive experience in semiconductor product life cycles and offers leadership opportunities, technical mentorship, and collaboration across global teams. **

Skills & Requirements

Must-have

  • 10-12 years DFT/DFD experience
  • Hierarchical DFT and Scan Compression
  • IEEE 1687 and IEEE 1838 standards
  • Multi-die chiplet system architecture
  • Silicon bring-up and failure analysis
  • Tessent or Synopsys EDA tool expertise

Nice-to-have

  • FPGA-specific configuration testing knowledge
  • ASIL-D functional safety standard experience
  • Mentoring senior engineering staff
  • Strategic stakeholder management skills
  • Python/Tcl scripting proficiency

Key Requirements

  • BS/MS/PhD in Electrical/Electronics/Computer Engineering
  • Minimum 10-12 years hands-on DFT/DFD experience
  • At least 4 years in an architectural or lead capacity
  • Expertise in ASIC and FPGA end-to-end product life cycle

Work Rights

Not specified

Tailored Resume

Cover Letter