Astera Labs is seeking a Senior Physical Design Engineer to lead the implementation of next-generation transceiver IPs targeting TSMC 5nm and 3nm nodes
Job Summary
Astera Labs is seeking a Senior Physical Design Engineer to lead the implementation of next-generation transceiver IPs targeting TSMC 5nm and 3nm nodes.
The role involves taking ownership of the full physical implementation flow from RTL to GDSII while ensuring timing and power closure for ultra-high-speed designs.
Candidates will collaborate with cross-functional teams to resolve challenges unique to advanced nodes and integrate diverse semiconductor technologies into cohesive systems.
Matching Summary
Match Score: 85
Astera Labs is seeking a Senior Physical Design Engineer to lead the implementation of next-generation transceiver IPs targeting TSMC 5nm and 3nm nodes.
Skills & Requirements
Must-have
TSMC 5nm or 3nm technology node experience
Full-chip physical implementation expertise
Timing closure and power optimization skills
Synopsys ICC2 and Cadence Innovus proficiency
High-speed SerDes and PHY integration experience
Nice-to-have
Advanced scripting in Tcl, Python, or Perl
Experience with multi-gigabit transceiver architectures
Knowledge of hierarchical design methodologies
Background in DSP or high-frequency data paths
Key Requirements
Bachelor's or Master's degree in Electrical Engineering
4+ years of experience in physical design
Hands-on experience with industry-standard verification tools